Non-volatile memory device and method for erasing the same

An erase method for a non-volatile memory device having vertical channel layers vertically formed on a semiconductor substrate with a greater upper width than a lower width, a pipe gate connecting lower ends of the vertical channel layers to each other, a source line and a bit line connected to an upper end of each of the vertical channel layers, a plurality of memory cells stacked to be spaced apart from each other along the vertical channel layers, and word lines connected to each of the memory cells, the method comprising:

• applying a preliminary erase voltage to the source line;
• applying an erase voltage higher than the preliminary erase voltage to the source line;
• erasing the memory cells while sequentially discharging the word lines beginning from the word lines positioned at an upper portion to the word lines positioned at a lower portion;
• and
• discharging the source line.

A non-volatile memory device, comprising:

• a memory cell array having a plurality of memory blocks including, vertical channel layers formed on a semiconductor substrate and having a greater upper width than a lower width, a pipe gate connecting lower ends of the vertical channel layers to each other, a source line and a bit line connected to an upper end of each of the vertical channel layers, a plurality of memory cells stacked to be spaced apart from each other along the vertical channel layers, and word lines connected to each of the memory cells;
• peripheral circuits suitable for performing an erase operation of a memory block selected out of the memory blocks;
• and
• a control circuit controlling the peripheral circuits to erase the memory cells while sequentially lowering potentials from the word lines positioned at an upper portion of the vertical channel layers during the erase operation.