Sram bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter

A system comprises:

• a memory unit;
• and
• a processor, coupled to the memory unit, the processor including cache memory comprising:
• a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used.

A level-shifter comprising:

• a first power supply to power a plurality of transistors of the level-shifter;
• a first input node to receive a first signal generated by a circuit operating on a second power supply, the second supply being different than the first power supply;
• a first n-type transistor to receive the first signal;
• a second input node to receive a second signal, which is an inverse of the first signal, the second signal generated by the circuit;
• and
• a second n-type transistor to receive the second signal, the first and second n-type transistors having drain terminals cross-coupled to some of the plurality of transistors.

A memory unit comprising:

• an array of memory cells;
• a column multiplexer coupled to the array of memory cells;
• a sense amplifier coupled to the column multiplexer;
• and
• an output data latch with integrated level-shifter includes:
• a first power supply to power a plurality of transistors of the level-shifter;
• a first input node to receive a first signal generated by a circuit operating on a second power supply, the second supply being different than the first power supply;
• a first n-type transistor to receive the first signal;
• a second input node to receive a second signal, which is an inverse of the first signal, the second signal generated by the circuit;
• and
• a second n-type transistor to receive the second signal, the first and second n-type transistors having drain terminals cross-coupled to some of the plurality of transistors.

An apparatus comprising:

• a write assist pulse generator operating on a first power supply;
• one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply;
• and
• an output node to provide power supply to a memory cell.