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US 2015/0146477 A1Published application
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsMasaaki IIJIMA, Nguyen Thein
Life of this patent
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Abstract
In order to solve a problem that a calibration period for generating a signal obtained by delaying a core clock in a programmable manner is overhead in initialization, a clock generation circuit generates a plurality of delayed clocks having different phases by delaying a core clock which is an operation clock of a CPU, and selects a resynchronization clock whose phase is later than and closest to a phase of a data strobe signal from among the generated delayed clocks and the core clock.
Claims10
A semiconductor device comprising:
- a first register for latching a data signal by a data strobe signal;
- a clock generation circuit for generating a resynchronization clock;
- and
- a second register for latching output data of the first register by the resynchronization clock,
- wherein the clock generation circuit generates a plurality of delayed clocks having different phases by delaying a core clock which is an operation clock of a CPU, and selects the resynchronization clock whose phase is later than and closest to a phase of the data strobe signal from among the generated delayed clocks and the core clock.
2 more elements
A semiconductor device comprising:
- a first register for latching a data signal by a data strobe signal;
- and
- an enable controller for generating an enable signal for controlling the latch of the data signal in the first register,
- wherein the first register comprises:
- a first flip-flop for latching the data signal by the data strobe signal;
- a second flip-flop for latching output of the first flip-flop by an inverted signal of the data strobe signal;
- a third flip-flop for latching the data signal by the inverted signal of the data strobe signal;
- and
- a clock gate for controlling supply of the inverted signal of the data strobe signal to the second flip-flop and the third flip-flop,
- wherein the clock gate is controlled by the enable signal, and
- wherein the enable controller activates the enable signal on a rising edge of a capture control signal whose period is identical to a period of the data strobe signal and whose phase is later than a phase of the data strobe signal, and deactivates the enable signal on a falling edge of the data strobe signal.
8 more elements
Dependencies are inferred from the claim text.