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US 2015/0146475 A1Published application
Memory sense amplifier with multiple modes of operation
AssigneeThe Regents of the University of Michigan
InventorsBharan GIRIDHAR, David Theodore BLAAUW, Dennis Michael SYLVESTER
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Abstract
Memory circuitry comprising an array of 6T bit cells 6 in which columns of bit cells are coupled together via bit line pairs 8 connected to respective sense amplifier circuitry 10 is provided. The sense amplifier circuitry includes an inverter pair 12, 14 and control circuitry which is configured to control the sense amplifier circuitry to operate in a plurality of modes including an offset compensation mode, an amplification mode and a latching mode.
Claims13
Memory circuitry comprising:
- an array of bit cells comprising a plurality of columns of bit cells;
- a plurality of bit lines pairs each coupled to a respective column of bit cells within said array;
- and
- sense amplifier circuitry coupled to at least one of said plurality of bit line pairs and configured to sense a voltage difference between bit lines of said at least one of said plurality of bit line pairs;
- wherein
- said sense amplifier circuitry comprises an inverter pair and control circuitry configured to control said sense amplifier circuitry to operate in a plurality of modes including:
- (i) an offset compensation mode in which said inverter pair is isolated from said bit lines and each inverter of said inverter pair adopts a state corresponding to a trip point at which an input voltage of said inverter is substantially equal to an output voltage of said inverter;
- (ii) an amplification mode in which each inverter of said inverter pair receives and amplifies a bit line voltage from a respective bit line of said bit line pair and said inverters of said inverter pair are isolated from each other;
- and
- (iii) a latching mode in which said inverter pair is cross-coupled so that an output of each inverter of said inverter pair is supplied as an input to another inverter of said inverter pair.
7 more elements
Memory circuitry comprising:
- an array of bit cell means for storing data comprising a plurality of columns of bit cell means;
- a plurality of bit lines pairs each coupled to a respective column of bit cell means within said array;
- and
- sense amplifier means for sensing a voltage difference between bit lines of said at least one of said plurality of bit line pairs;
- wherein
- said sense amplifier means comprises an inverter pair and control means for controlling said sense amplifier means to operate in a plurality of modes including:
- (i) an offset compensation mode in which said inverter pair is isolated from said bit lines and each inverter of said inverter pair adopts a state corresponding to a trip point at which an input voltage of said inverter is substantially equal to an output voltage of said inverter;
- (ii) an amplification mode in which each inverter of said inverter pair receives and amplifies a bit line voltage from a respective bit line of said bit line pair and said inverters of said inverter pair are isolated from each other;
- and
- (iii) a latching mode in which said inverter pair is cross-coupled so that an output of each inverter of said inverter pair is supplied as an input to another inverter of said inverter pair.
7 more elements
A method of reading data from memory circuitry comprising:
- an array of bit cells comprising a plurality of columns of bit cells;
- a plurality of bit lines pairs each coupled to a respective column of bit cells within said array;
- and
- sense amplifier circuitry coupled to at least one of said plurality of bit line pairs and configured to sense a voltage difference between bit lines of said at least one of said plurality of bit line pairs;
- said method comprising the step of:
- operating said sense amplifier circuitry in an offset compensation mode in which said inverter pair is isolated from said bit lines and each inverter of said inverter pair adopts a state corresponding to a trip point at which an input voltage of said inverter is substantially equal to an output voltage of said inverter;
- operating said sense amplifier circuitry in an amplification mode in which each inverter of said inverter pair receives and amplifies a bit line voltage from a respective bit line of said bit line pair and said inverters of said inverter pair are isolated from each other;
- and
- operating said sense amplifier circuitry in a latching mode in which said inverter pair is cross-coupled so that an output of each inverter of said inverter pair is supplied as an input to another inverter of said inverter pair.
6 more elements
Dependencies are inferred from the claim text.