Memory device and method of controlling memory device

A memory device comprising:

• a plurality of global column lines arranged in parallel and extending in a first direction;
• a plurality of row lines extending in a second direction which is perpendicular to the first direction;
• a plurality of column lines in a two-dimensional arrangement, which extend in a third direction which is perpendicular to the first direction and the second direction;
• a memory cell array including a plurality of memory cells each including a resistance change material, the memory cells being arranged at intersections between the row lines and the column lines;
• a plurality of sheet selectors disposed between the global column lines and the column lines;
• and
• a controller configured to control the global column lines, the row lines, the column lines, the memory cells and the sheet selectors,
• the plurality of sheet selectors comprising:
• a first transistor including a channel region, a first insulation layer formed on a first side surface of the channel region, and a first select gate line extending in the second direction and formed on the first insulation layer in the first direction;
• and
• a second transistor including a channel region, a second insulation layer formed on a second side surface of the channel region, which is opposed to the first side surface in the first direction, and a second select gate line extending in the second direction and formed on the second insulation layer in the first direction, and
• the controller being configured, at a time of storing or easing data in the memory cell array, to execute:
• select a global column line, a row line and a select gate line in order to select the memory cells;
• apply a select row line voltage to a selected row line of the plurality of row lines;
• apply a non-select row line voltage to a non-selected row line of the plurality of row lines;
• apply a select global column line voltage to a selected global column line of the plurality of global column lines;
• apply a first non-select global column line voltage to a non-selected global column line of the plurality of global column lines;
• apply a non-select selector voltage to the first and second select gate lines;
• apply a first select selector voltage to the first select gate line of the first transistor of a selected sheet selector of the plurality of sheet selectors;
• and
• apply, after passage of a first time after the applying of the first select selector voltage, a second select selector voltage to the second select gate line of the selected sheet selector.