Resistive memory apparatus and write-in method thereof

A resistive memory apparatus, comprising:

• a memory cell array, comprising a plurality of memory unit, wherein each of the memory units comprises a plurality of stacked resistive memory cells, the resistive memory cells are respectively coupled to a plurality of word-lines and the memory units are respectively coupled to a plurality of bit-lines;
• and
• a memory controller, coupled to the memory cell array, wherein,
• the memory controller provides a plurality of unselected bit-lines not coupled to a selected resistive memory cell with a first bit-line voltage and a plurality of unselected word-lines not coupled to the selected resistive memory cell with a first word-line voltage in one of a setting duration and a resetting duration, wherein the first bit-line voltage is equal to a product of a writing-in voltage VW and (n−1)/n and the first word-line voltage is equal to VW×1/n wherein n is a real number greater than 3,
• the memory controller provides the unselected bit-lines not coupled to the selected resistive memory cell with a second bit-line voltage and the unselected word-lines not coupled to the selected resistive memory cell with a second word-line voltage in the other one of the setting duration and the resetting duration, wherein the second bit-line voltage is equal to VW×1/n and the second word-line voltage is equal to VW×(n−1)/n.