Anti-fuse array of semiconductor device and method for operating the same
AssigneeSK hynix Inc.
InventorSung Su KIM
Life of this patent
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Abstract
An anti-fuse array includes: a plurality of first transistors having a matrix structure over a semiconductor substrate; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure; and a plurality of third transistors respectively disposed at second ends of the plurality of first transistors along a second direction.
Claims20
An anti-fuse array comprising:
- a plurality of first transistors having a matrix structure over a semiconductor substrate, the plurality of first transistors including a plurality of gate lines extending along a first direction, a plurality of channel lines extending along a second direction;
- a plurality of second transistors respectively disposed adjacent to first ends of the plurality of gate lines;
- and
- a plurality of third transistors respectively disposed at second ends of the plurality of channel lines.
A method for operating an anti-fuse array which includes a plurality of first transistors formed as a matrix structure over a semiconductor substrate, a plurality of second transistors respectively formed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure, and a plurality of third transistors respectively formed at second ends of the plurality of first transistors along a second direction, the method comprising:
- applying a first voltage to the plurality of first transistors using a first transistor among the plurality of second transistors;
- applying a second voltage to the plurality of first transistors using a second transistor among the plurality of third transistors;
- and
- rupturing a third transistor among the first plurality of transistors located at an intersection of a gate line coupled to the first transistor and a channel line coupled to the second transistor due to a voltage level difference across a gate insulation film of the third transistor corresponding to a difference between the first voltage and the second voltage.
Dependencies are inferred from the claim text.