US 2015/0145709 A1 · N-Path Interleaving Analog-to-Digital Converter (ADC) with Background Calibration

Abstract

A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s1(t) is accepted having a first frequency f1 and a bandwidth (BW). A clock at frequency fs creates n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. A first tone signal s2(t) is generated at second frequency f2, outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating n digital sample signals per clock period 1/fs. The n digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information for a rotating pair of digital sample signals.

Claims22

Dependent claims

A method of performing background corrections for an n-path interleaving analog-to-digital converter (ADC), the method comprising:

accepting an analog input signal s1(t) having a first frequency f1 and a bandwidth (BW);
generating a clock having a clock frequency fs;
creating n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/n, where n is an integer greater than 2;
generating a first tone signal s2(t) having a predetermined second frequency f2 outside BW;
combining the analog input signal and the first tone signal, creating a combination signal;
sampling the combination signal using the n sample clocks, creating n digital sample signals per clock period 1/fs;
interleaving the n digital sample signals, creating an interleaved signal;
applying corrections that minimize errors in the interleaved signal to obtain a corrected digital output;
and,
for a pair of digital sample signals, determining errors at an alias frequency f3, associated with the second frequency f2, to obtain correction information.

7 more elements

A system performing background corrections for an n-path interleaving analog-to-digital converter (ADC), the system comprising:

a first summing circuit having an input to accept an analog input signal s1(t) with a first frequency f1 and a bandwidth (BW), an input to accept a first tone signal s2(t) having a predetermined second frequency f2 outside BW, and an output to supply a combination signal;
a clock having a clock frequency fs, with outputs to supply n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/n, where n is an integer greater than 2;
an interleaving ADC having inputs to accept the combination signal and the n sample clocks, the interleaving ADC creating n digital sample signals in response to sampling the combination signal with the n sample clocks, and supplying an interleaved signal at an output;
an error correction module having an input to accept the interleaved signal and an input to accept correction information, the error correction module applying corrections that minimize errors in the interleaved signal, and supplying a corrected digital output;
and,
an error estimation module having an input to accept the corrected digital output, the error estimation module determining errors at an alias frequency f3, associated with the second frequency f2, for a pair of digital sample signals, and supplying correction information at an output for a first digital sample signal.

3 more elements

Dependencies are inferred from the claim text.

N-Path Interleaving Analog-to-Digital Converter (ADC) with Background Calibration

Life of this patent

N-Path Interleaving Analog-to-Digital Converter (ADC) with Background Calibration

Life of this patent

Abstract

Claims22