Semiconductor package
AssigneeMedia Tek Inc.
InventorsTai-Yu CHEN, Chung-Fa LEE, Wen-Sung HSU, Shih-Chin LIN
Life of this patent
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AssigneeMedia Tek Inc.
InventorsTai-Yu CHEN, Chung-Fa LEE, Wen-Sung HSU, Shih-Chin LIN
Estimating the term…
A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.
A semiconductor package, comprising:
Dependencies are inferred from the claim text.