Methods for Deep Trench MIM Capacitor Moat Isolation with N+ Epitaxial Semiconductor Wafer Scheme
AssigneeInternational Business Machines Corporation
InventorsThomas Walter Dyer, Herbert Lei Ho, Jin Liu
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Abstract
An integrated circuit structure provides at least one metal-insulator-metal (MIM) capacitor and a moat isolation structure wherein the number of processes required is substantially minimized and the formation of the MIM capacitor and the moat isolation structure effectively decouple while the number of processes common to the moat isolation structure and the MIM capacitor are maximized. Additional required processes are non-critical and tolerant of overlay positioning error.
Claims20
An integrated circuit structure comprising an array area including an MIM capacitor,
- a support area, and
- a moat isolation structure between said array area and said support area, wherein said moat isolation structure extends farther into a substrate than said MIM capacitor and is formed by an insulator lining in a trench and filled with a fill material comprising one of
- a further insulator and
- an insulator layer and one or more layers in common with said MIM capacitor.
A method of manufacture of an integated circuit structure comprising a moat isolation structure and a MIM capacitor, said method comprising steps of
- forming respective recesses for said moat isolation structure and said MIM capacitor,
- depositing a material in said respective recesses, and
- if said material deposited in said respective recesses is a conductor, removing said conductor from said recess for said moat isolation structure and depositing an insulator, or
- if said material deposited in said respective recesses is an insulator, removing said material from said recess for said MIM capacitor, and
- completing said integrated circuit structure by forming said MIM capacitor and filling any unfilled portion of said recess for said moat isolation structure.
Dependencies are inferred from the claim text.