Vertical-type semiconductor apparatus and fabrication method thereof

A vertical-type semiconductor apparatus, comprising:

• a semiconductor substrate including first and second regions;
• one or more channel pillars vertically extending from the semiconductor substrate of the first region;
• one or more insulating pillars vertically extending from the semiconductor substrate of the second region;
• an inactive region formed to surround lower ends of the channel and insulating pillars;
• a gate conductive layer formed on the inactive region and surrounding the channel and insulating pillars;
• and
• a gate contact formed on at least one of the insulating pillars to be coupled to the gate conductive layer,
• wherein the at least one of the insulating pillars has a height lower than the gate conductive layer and higher than the surface of the semiconductor substrate.

A method of fabricating a vertical-type semiconductor apparatus, the method comprising:

• forming an inactive region having a first depth in a semiconductor substrate and formed from a surface thereof;
• forming hard mask patterns on the semiconductor substrate including the inactive region and forming a plurality of pillars by patterning the semiconductor substrate and the inactive region to a second depth;
• forming a gate conductive layer on an outer circumference of each of the plurality of pillars;
• forming a first insulating layer on the semiconductor substrate including the gate conductive layer and planarizing the first insulating layer;
• forming a gate contact hole by removing at least one of pillars formed on the inactive region to have a height lower than the gate conductive layer;
• and
• forming a gate contact by burying a conductive material in the gate contact hole.

A method of fabricating a vertical-type semiconductor apparatus, the method comprising:

• forming hard mask patterns on a semiconductor substrate in which a first region and a second region are defined, and forming a plurality of pillars by patterning the semiconductor substrate;
• forming an inactive region of a first height to surround a lower end of each of the plurality of pillars;
• forming a gate conductive layer of a second height on the inactive region to surround the pillar;
• forming an insulating layer on the semiconductor substrate including the gate conductive layer and planarizing the insulating layer;
• forming a gate contact hole by etching at least one of pillars formed in the second region to have a height lower than the gate conductive layer;
• and
• forming a gate contact by burying a conductive material in the gate contact hole.