Nonvolatile memory device
AssigneeSK hynix Inc.
InventorSung-Kun PARK
Life of this patent
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Abstract
A nonvolatile memory device may include: an isolation layer formed in a substrate and defining an active region; a control plug formed over the isolation layer; a floating gate formed over the substrate and including a plurality of fingers adjacent to the control plug with a gap provided therebetween; and a charge blocking layer formed on sidewalls of the floating gate so as to fill the gap. The control plug may include: a first control plug formed between the plurality of fingers and having sidewalls facing inner walls of the fingers; and a second control plug formed outside the floating gate and having sidewalls facing outer walls of the fingers.
Claims18
A nonvolatile memory device comprising:
- an isolation layer formed in a substrate and defining an active region;
- a control plug formed over the isolation layer;
- a floating gate formed over the substrate and comprising a plurality of fingers adjacent to the control plug with a gap provided therebetween;
- and
- a charge blocking layer formed on sidewalls of the floating gate so as to fill the gap,
- wherein the control plug comprises:
- a first control plug formed between the plurality of fingers and having sidewalls facing inner walls of the fingers;
- and
- a second control plug formed outside the floating gate and having sidewalls facing outer walls of the fingers.
The nonvolatile memory device of claim further comprising:
- a well formed in the substrate;
- a well tap defined by the isolation layer;
- and
- a select gate formed over the active region.
A nonvolatile memory device comprising a cell array in which a plurality of unit cells are two-dimensionally arranged,
- wherein each of the unit cells comprises:
- a well formed in a substrate;
- an isolation layer formed in the substrate and defining an active region;
- a control plug formed over the isolation layer;
- a floating gate formed over the substrate and comprising a plurality of fingers adjacent to the control plug with a gate provided therebetween;
- and
- a charge blocking layer formed on the sidewalk of the floating gate so as to fill the gap,
- wherein the cell array comprises:
- a memory set comprising two unit cells sharing one active region in a first direction and the well tap positioned at both ends thereof;
- and
- a plurality of memory groups each comprising the plurality of memory sets arranged to be separated at a predetermined interval from each other in a second direction crossing the first direction, and
- the plurality of memory groups are arranged to be symmetrical with each other, based on the well tap.
Dependencies are inferred from the claim text.