US 2015/0145009 A1Published application

Semiconductor integrated circuit device and manufacturing method thereof

AssigneeRenesas Electronics Corporation

InventorSeigo NAMIOKA

Life of this patent

Estimating the term…

Loading patent…

Abstract

In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR1. The eDRAM further includes: a capacitive plug electrode coupled to the drain plug electrode; a bit line coupled to the source plug electrode; a stopper film covering the bit line; and a capacitive element that is formed over the stopper film and has a first electrode, a dielectric film, and a second electrode. The first electrode is coupled to the capacitive plug electrode, and the height of the capacitive plug electrode and that of the bit line are equal to each other.

Claims19

Dependent claims

A semiconductor integrated circuit device comprising:

a semiconductor substrate;
a word line extending in a first direction in a main surface of the semiconductor substrate;
a bit line extending in a second direction that intersects with the first direction in the main surface of the semiconductor substrate;
a gate electrode that is formed in the main surface of the semiconductor substrate and serves as the word line;
a MISFET having a source region and a drain region that are formed in the main surface of the semiconductor substrate so as to sandwich the gate electrode;
a first interlayer insulating film that is formed over the main surface of the semiconductor substrate so as to cover the MISFET;
a source plug electrode that penetrates the first interlayer insulating film to be electrically coupled to the source region;
a drain plug electrode that penetrates the first interlayer insulating film to be electrically coupled to the drain region;
a second interlayer insulating film formed over the first interlayer insulating film;
a capacitive plug electrode that penetrates the second interlayer insulating film to be electrically coupled to the drain plug electrode;
the bit line that penetrates the second interlayer insulating film to be electrically coupled to the source plug electrode;
a first insulating film covering the bit line;
and
a capacitive element that is formed over the first insulating film and has a first electrode, a dielectric film, and a second electrode,
wherein the first electrode is electrically coupled to the capacitive plug electrode,
and wherein a height of the capacitive plug electrode and that of the bit line are equal to each other.

13 more elements

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

(a) forming, in a main surface of a semiconductor substrate, a MISFET having a gate electrode, a source region, and a drain region;
(b) forming a first interlayer insulating film over the main surface of the semiconductor substrate so as to cover the MISFET;
(c) after a first contact hole for exposing the source region or the drain region is formed in the first interlayer insulating film, forming a source plug electrode coupled to the source region or a drain plug electrode coupled to the drain region in the first contact hole;
(d) forming a second interlayer insulating film over the first interlayer insulating film;
(e) forming both a second contact hole in the second interlayer insulating film so as to expose an upper surface of the drain plug electrode and a wiring trench in the second interlayer insulating film so as to expose an upper surface of the source plug electrode;
(f) forming both a capacitive plug electrode in the second contact hole and a bit line in the wiring trench;
(g) forming, over the bit line, an insulating film having a first opening for exposing an upper surface of the capacitive plug electrode;
(h) forming, over the insulating film, a third interlayer insulating film having a second opening for exposing the upper surface of the capacitive plug electrode;
and
(i) forming a first electrode, a dielectric film, and a second electrode in this order in the second opening,
wherein the first electrode, the dielectric film, and the second electrode form a capacitive element, and the first electrode is electrically coupled to the capacitive plug electrode.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/531,336Filed 3 Nov 2014
Priority: JP 2013-24422426 Nov 2013
Published: 28 May 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 12/315
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10D 64/254
Source or drain electrodes for field-effect devices: for lateral devices wherein the source or drain electrodes extend entirely through the…

Family

US 9,305,925 B2Related patent
US 2015/0145009 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key