CMOS Devices with Reduced Leakage and Methods of Forming the Same

A device comprising:

• a silicon substrate;
• a silicon germanium layer having a first germanium percentage;
• a silicon layer over the silicon germanium layer;
• a silicon germanium region having a bottom surface over and contacting a first top surface of the silicon layer, wherein the silicon germanium region has a second germanium percentage higher than the first germanium percentage;
• a P-type Metal-Oxide-Semiconductor (PMOS) device comprising:
• a first gate dielectric over the silicon germanium region;
• an N-type Metal-Oxide-Semiconductor (NMOS) device comprising:
• a second gate dielectric over a second top surface of the silicon layer;
• and
• a source/drain region adjacent to the second gate dielectric;
• a first Shallow Trench Isolation (STI) region in the silicon layer, wherein the first STI region contacts the source/drain region;
• and
• a first silicon germanium oxide region in the silicon germanium layer, the first silicon germanium oxide region comprising:
• a first portion underlying and contacting the first STI region;
• and
• a second portion overlapped by the source/drain region of the NMOS device.

A method comprising:

• performing a first epitaxy to form a silicon germanium layer over a substrate, wherein the silicon germanium layer has a first germanium percentage;
• performing a second epitaxy to form a silicon layer over the silicon germanium layer;
• etching the silicon layer to form a trench, with a bottom portion of silicon layer left under the trench, wherein the bottom portion of the silicon layer has a top surface comprising a first slanted portion, with the first slanted portion comprising a (551) plane of the silicon layer;
• performing a third epitaxy to form a silicon germanium region in the trench, wherein the silicon germanium region has a bottom surface over and contacting the top surface of the silicon layer;
• and
• forming a P-type Metal-Oxide-Semiconductor (PMOS) device comprising:
• forming a first gate dielectric over a top surface of the silicon germanium region, with a channel region of the PMOS device in the silicon germanium region.