Integrated circuits with shallow trench isolations, and methods for producing the same
AssigneeGlobalfoundries Inc.
InventorsRan Yan, Nicolas Sassiat, Alban Zaka, Kun-Hsien Lin
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Abstract
Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.
Claims20
A method of producing an integrated circuit comprising:
- forming a trench in a substrate, wherein the trench comprises a trench surface;
- forming a barrier layer overlying the trench surface, wherein the barrier layer comprises silicon and germanium;
- and
- forming a shallow trench isolation by forming a core overlying the barrier layer, wherein the core comprises a shallow trench isolation insulator.
A method of producing an integrated circuit comprising:
- forming a shallow trench isolation in a substrate, wherein the shallow trench isolation comprises a barrier layer adjacent to the substrate, and wherein the barrier layer comprises germanium;
- forming an embedded plug trough in the substrate adjacent to the barrier layer;
- and
- forming an embedded plug in the embedded plug trough such that the embedded plug contacts the barrier layer, wherein the embedded plug comprises silicon and germanium.
An integrated circuit comprising:
- a substrate;
- a shallow trench isolation embedded within the substrate, wherein the shallow trench isolation comprises a core overlying a barrier layer such that the barrier layer is adjacent to the substrate, wherein the core comprises a shallow trench isolation insulator, and wherein the barrier layer comprises germanium;
- a transistor gate overlying the substrate;
- and
- a source and a drain embedded within the substrate, wherein the source and the drain comprise silicon and germanium, wherein the source and the drain are positioned on opposite sides of the transistor gate, and wherein one of the source and the drain contacts the barrier layer.
Dependencies are inferred from the claim text.