Thin film transistor array panel and method for manufacturing the same

A thin film transistor array panel, comprising:

• an insulating substrate;
• a gate line on the insulating substrate and comprising a gate electrode;
• a reference electrode line on the insulating substrate, separated from the gate line and comprising an extension;
• a first gate insulating layer on the insulating substrate, the gate line and the reference electrode line;
• a semiconductor layer on the first gate insulating layer and overlapping the gate electrode;
• a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and a semiconductor opening defined in the second gate insulating layer and through which the semiconductor layer is exposed;
• a data line comprising a source electrode;
• a drain electrode on the second gate insulating layer and the semiconductor layer, and facing the source electrode;
• a first passivation layer on the data line, the drain electrode and the second gate insulating layer;
• a second passivation layer on the first passivation layer;
• a first field generating electrode on the second passivation layer;
• a third passivation layer on the first field generating electrode;
• a first contact hole defined in the first passivation layer, the second passivation layer and the third passivation layer and exposing the drain electrode;
• and
• a second field generating electrode on the third passivation layer and connected to the drain electrode through the first contact hole,
• wherein
• the semiconductor layer comprises an oxide semiconductor layer, and a first auxiliary layer and a second auxiliary layer disposed on the oxide semiconductor layer and separated from each other,
• an edge of the drain electrode exposes an edge of the first auxiliary layer in a plan view, and
• an edge of the source electrode exposes an edge of the second auxiliary layer in the plan view.