Memory Arrays and Methods of Forming Memory Cells

32:

• A method of forming a plurality of memory cells and select devices, comprising:
• forming a stack which comprises, in ascending order, a homogeneous n-type doped region, a p-type doped region and an ovonic material;
• patterning the stack into rails which extend along a first direction and which are spaced from one another by first trenches;
• patterning the rails into pillars, the patterning into the pillars comprising etching into but not entirely through the homogeneous n-type doped region to form a portion of the homogeneous n-type doped region into segments within the pillars, and to leave some of the homogeneous n-type doped region as first conductive lines interconnecting the pillars along the first direction;
• the patterning forming second trenches which extend along a second direction that intersects the first direction;
• the p-type doped region and the segments of the homogeneous n-type doped region being incorporated into vertical select devices within the pillars;
• and
• forming second electrically conductive lines over the ovonic material, with the second electrically conductive lines extending along the second direction;
• the second electrically conductive lines interconnecting the pillars along the second direction.

39:

• A method of forming a plurality of memory cells, comprising:
• forming a stack over a semiconductor base;
• the stack comprising, in ascending order from the substrate, a homogeneous n-type doped region, a p-type doped region and an ovonic material;
• patterning the stack into rails, with the rails extending along a first direction, the rails being spaced from one another by first trenches;
• patterning the rails into pillars, the patterning into the pillars comprising etching into but not entirely through the homogeneous n-type doped region to form a portion of the homogeneous n-type doped region into segments within the pillars, and to leave some of the homogeneous n-type doped region as first conductive lines interconnecting the pillars along the first direction;
• the patterning forming second trenches which extend along a second direction that intersects the first direction;
• the p-type doped region and the segments of the homogeneous n-type doped region being incorporated into vertical select devices within the pillars;
• and
• forming second electrically conductive lines over the ovonic material, with the second electrically conductive lines extending along the second direction;
• the second electrically conductive lines interconnecting the pillars along the second direction.

43:

• A memory array, comprising:
• first electrically conductive lines, the first electrically conductive lines being n-type doped regions of semiconductor material and extending along a first direction;
• pillars over the first conductive lines;
• the pillars comprising mesas of the n-type doped regions of the semiconductor material extending upwardly from the electrically conductive lines, comprising carbon-containing barrier material over the semiconductor material of the mesas, comprising p-type doped regions over the barrier material, and comprising ovonic material over the p-type doped regions;
• wherein a common, continuous and homogenous n-type doped semiconductor material comprises both the n-type doped regions of the first electrically conductive lines and the mesas of the n-type doped regions;
• the p-type doped regions and the mesas of the n-type doped regions being incorporated into vertical select devices within the pillars;
• and
• second electrically conductive lines over the ovonic material;
• the second electrically conductive lines extending along a second direction that intersects the first direction;
• the second electrically conductive lines interconnecting the pillars along the second direction.