Data processor and data processing system

A semiconductor integrated circuit provided on a semiconductor chip, the semiconductor integrated circuit comprising:

• an external reset terminal used for outputting a system reset signal to outside of the semiconductor integrated circuit and for receiving an external reset signal from outside of the semiconductor integrated circuit;
• an input/output buffer coupled to the external reset terminal,
• wherein the input/output buffer is able to output the system reset signal to outside of the semiconductor integrated circuit through the external reset terminal, and is able to receive the external reset signal from outside of the semiconductor integrated circuit through the external reset terminal and generate an internal received reset signal;
• a detection circuit which detects respective reset factors including a first reset factor due to turn-on of a power supply and a second reset factor due to a voltage drop of the power supply, and generates a detection signal;
• a reset controller which generates the system reset signal, based on the detection signal from the detection circuit and the internal received reset signal generated by the input/output buffer, and, when the system reset signal generated based on the detection signal from the detection circuit is output to the outside of the semiconductor integrated circuit through the input/output buffer and the external reset terminal, enables the input/output buffer to output the system reset signal and masks the internal received reset signal generated by the input/output buffer during a first period which includes and is longer than a second period from the time of asserting the system reset signal to the time of releasing the system reset signal;
• and
• a CPU initialized based on the system reset signal.

The semiconductor integrated circuit according to claim 1,

• wherein the reset controller disables the input/output buffer output of the system reset signal and stops masking the internal received reset signal at a timing delayed from the time of releasing the system reset signal after an elapse of a reset hold period when the reset factor due to the turn-on of the power supply is detected, and generates the system reset signal synchronized with the internal received reset signal inputted from the external reset terminal during a period that none of the reset factors are detected after the time of releasing the system reset signal generated based on the reset factor due to the turn-on of the power supply, and
• wherein the reset controller enables the input/output buffer to output the system reset signal and masks the internal received reset signal generated by the input/output buffer when the reset factor due to the voltage drop of the power supply is detected after the time of releasing the system reset signal generated based on the reset factor due to the turn-on of the power supply and then the reset controller asserts the system reset signal and after an elapse of a reset hold period releases the system reset signal being output through the external reset terminal, and then disables the input/output buffer output of the system reset signal and stops masking the internal received reset signal.