US 2015/0106602 A1 · RANDOMLY BRANCHING USING HARDWARE WATCHPOINTS

Abstract

A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. The processor allocates a memory region for the purpose of creating “random branches” in the computer code utilizing existing memory access instructions. When the processor processes a given instruction, the processor both accesses a first location in the memory region and may determine a condition is satisfied. In response, the processor generates an interrupt. The corresponding interrupt handler may transfer control flow from the computer program to instrumentation code. The condition may include a pointer storing an address pointing to locations within the memory region equals a given address after the point is updated. Alternatively, the condition may include an updated data value stored in a location pointed to by the given address equals a threshold value.

Claims20

Dependent claims

A computing system comprising:

a memory configured to store a computer program;
a processor coupled to the memory, wherein the processor is configured to:
process instructions of the stored computer program;
and
allocate in the memory a memory region comprising a plurality of locations;
and
responsive to determining a predetermined instruction is being processed in a predetermined pipeline stage:
forego processing of instructions following the predetermined instruction and process the instrumentation code, in response to determining both the predetermined instruction accesses a first location of the plurality of locations and a condition is satisfied.

5 more elements

A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable to:

processing instructions of a computer program stored in a memory;
allocating in the memory a memory region comprising a plurality of locations;
responsive to determining a predetermined instruction is being processed in a predetermined pipeline stage:
forego processing of instructions following the predetermined instruction and process the instrumentation code, in response to determining both the predetermined instruction accesses a first location of the plurality of locations and a condition is satisfied.

1 more element

Dependencies are inferred from the claim text.

Randomly branching using hardware watchpoints

Life of this patent

Randomly branching using hardware watchpoints

Life of this patent

Abstract

Claims20