Data Processing System Having Integrated Pipelined Array Data Processor
AssigneePact Xpp Technologies AG
InventorsMartin Vorbach, Jürgen Becker, Markus Weinhardt, Volker Baumgarte, Frank May
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Abstract
A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.
Claims13
A data processing system, comprising:
- a memory;
- a data processor core adapted for processing software threads;
- and
- an integrated array data processor for processing imaging algorithms;
- the integrated array data processor having
- i) an array of programmable arithmetic execution units,
- ii) a unit for loading algorithms to the array of programmable arithmetic execution units;
- and
- a plurality of pipeline stages for processing data;
- and
- a joint cache shared between the data processor core and the array data processor;
- the cache being connected to the memory;
- the data processing system further including:
- a buffer for storing a list algorithms to be loaded by the unit for loading algorithms, the list being generated by the data processor core.
A data processor device comprising:
- a data processor core adapted for processing software threads having a plurality of data load units;
- at least one array data processor having an array of programmable arithmetic execution units, the array data processor adapted for processing software threads in accordance with instruction dispatch data;
- and
- a multi-level cache for caching instructions and data, at least one level of the multi-level cache comprising a plurality of cache slices, the multi-level cache being shared by the data processor core and the array data processor;
- an instruction decoder decoding instructions so information how to process data can be provided to an instruction dispatch unit separate from the data processor core.
A multi-core processor comprising:
- a plurality of processing units;
- one 1st level instruction cache shared by the processing units;
- one shared instruction fetch unit supplying the processing units jointly with instructions from the instruction cache;
- and
- each of the processing units having:
- a separate instruction fetch and decode unit;
- and
- an execution unit path comprising a plurality of arithmetic units;
- and
- at least one data cache being shared by the at least two processing units.
The multi-core processor according to the previous claim, wherein the at least one of the two processing units having a dedicated 1st level data cache sharing a higher cache level with at least one other of the at least two processing units.
The multi-core processor according to the previous claim, wherein one of the plurality of processing units has a dedicated 1st level data cache sharing at least the 2nd level cache with at least one other of the plurality of processing units.
Dependencies are inferred from the claim text.