Chip stack cache extension with coherency
AssigneeInternational Business Machines Corporation
InventorsEdgar R. Cordero, Anand Haridass, Subrat K. Panda, Saravanan Sethuraman, Diyanesh Babu Chinnakkonda Vidyapoornachary
Life of this patent
Estimating the term…
Abstract
By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.
Claims20
A cache management method for a semiconductor device stack of at least two dies, each die including at least two computing devices, each computing device including at least one core, each core including a local cache, and each die including at least one shared cache connected to at least one core of the respective die, the method comprising:
- testing each core;
- responsive to a core failing the testing, identifying the core as a failed core;
- responsive to a core passing the testing, identifying the core as a good core;
- stacking the at least two dies such that a good core of a first die is aligned with a failed core of at least one adjacent die;
- and
- connecting a failed core local cache of each failed core to at least a first aligned good core for primary use by the at least a first aligned good core.
A semiconductor device stack comprising:
- at least two dies, each die including:
- at least two computing devices, each computing device including:
- at least one core having associated therewith a respective identifier of good core or failed core;
- and
- a respective local cache connected to each core;
- at least one shared cache connected to every core of the computing device;
- and
- a configuration register connected to every core of the computing device and storing each respective identifier in a respective quality indicator,
- wherein the at least two dies are oriented with any failed core of any die aligned with a respective good core of at least one other adjacent die,
- the stack being configured to enter a cache extension mode in which at least one good core is configured to use at least one of a local cache of another core or a shared cache of another computing device.
A method comprising:
- testing each of at least two dies each including at least one computing device with at least one respective core, each core having a respective local core, and each die having at least one shared cache connected to at least one respective core;
- storing a quality indicator for each core in at least one configuration register, the quality indicator identifying the respective core as a failed core or as a good core responsive to the respective core failing or passing the testing, respectively;
- stacking the dies with any failed core in alignment with a respective good core of at least one adjacent die;
- determining a first latency between a good core and the respective shared cache;
- determining a second latency between the good core and the local cache of a failed core;
- and
- connecting the local cache of the good core to the respective one of the local cache or the shared cache associated with the lesser of the first latency and the second latency.
Dependencies are inferred from the claim text.