Managed-NAND With Embedded Random-Access Non-Volatile Memory

A method comprising:

• reading a first portion of boot code from an internal read-only memory (ROM) of a host processor to initiate a boot sequence;
• identifying a location of a second portion of the boot code;
• issuing read commands from the host processor to a managed-NAND memory controller having an embedded random-access non-volatile memory, array;
• executing the read commands in the embedded random-access non-volatile memory array;
• and
• completing the boot sequence.

A method comprising:

• reading a first portion of boot code from an internal read-only memory (ROM) of a host processor;
• identifying a second portion of the boot code;
• copying a first portion of the second portion of the boot code from a managed-NAND memory controller to external volatile memory;
• issuing read commands, using the host processor, to the external volatile memory;
• executing the read commands for the first portion of the second portion of the boot code in the external volatile memory;
• completing the boot sequence for the first portion of the second portion of the boot code;
• issuing read commands from the host processor to a managed-NAND memory system for a second portion of the second portion of the boot code;
• executing the read commands for the second portion of the second portion of the boot code in a random-access non-volatile memory array embedded in the managed-NAND memory system;
• and
• completing the boot sequence for the second portion of the second portion of the boot code.

A method comprising:

• providing an application processor coupled to an external volatile memory and a managed-NAND memory system comprising an embedded random-access non-volatile memory array;
• mapping the address of the embedded random-access non-volatile memory array into an address map of a memory controller of the managed-NAND memory system;
• partitioning an application into a latency-critical portion and a latency-non-critical portion;
• storing the latency-critical portion in the embedded random-access non-volatile memory array and the latency-non-critical portion in a NAND memory array;
• issuing a read command from the application processor to the memory controller of the managed-NAND system;
• copying a data content of the latency-non-critical portion from a NAND memory array in the managed-NAND memory system to the external volatile memory;
• reading the latency-critical portion of the application in the embedded random-access non-volatile memory;
• and
• reading the latency-non-critical portion of the application in the external volatile memory.