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US 2015/0106414 A1Published application
System and method for improved fractional binary to fractional residue converter and multipler
AssigneeOlsen IP Reserve, LLC
InventorEric B. Olsen
Life of this patent
Estimating the term…
Abstract
Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.
Claims5
A residue number normalization unit comprising:
- a plurality of digit processing units that perform one or more modular arithmetic operations on one or more operands to generate an output within a predefined modulus value, wherein the modular arithmetic operations do not result in a carry value;
- a common data bus that transmits data to and from each of the plurality of digit processing units;
- a digit power multiplier that receives a mixed radix digit and an associated digit power value, and transmit a resulting weighted digit power product, the multiplier coupled to the digit power accumulator;
- a digit power accumulator that receives and accumulate weighted digit power products, the accumulator coupled to a result selector;
- a controller that transmits one or more commands to instruct one or more of the plurality of digit processing units to:
- convert one or more residue numbers having at least a fractional representation to a plurality of digits in mixed radix format;
- receive one or more mixed radix digits, each digit associated with a mixed radix power, and multiplying the digit value by the associated mixed radix power, thereby forming a weighted digit power product;
- and
- sum a selected portion of the plurality of weighted digit power products;
- wherein said result selector, responsive to one or more controller commands, transmits a result from among one or more candidate normalization values.
7 more elements
A residue converter configured to convert a fractional binary value to a fractional residue value comprising:
- an input register that receives a plurality of binary input digits, the plurality of binary input digits configured as a parallel binary input receiving a binary fractional value;
- a modulus shift register that stores a plurality of modulus values and to output each of the plurality of modulus values in sequence;
- a first plurality of digit processing units that performs one or more arithmetic operations on a plurality of binary input digits and on a sequence of modulus values, and to generate a plurality of digit values and modulus values, each digit processing unit comprising:
- a modulus operand register that receives a modulus value from a prior processing stage, and configured to send a modulus value to a succeeding processing stage;
- an additive operand register that receives a digit value from a prior processing stage;
- a digit accumulator that stores a binary digit value;
- a multiplier that multiplies the contents of said digit accumulator with the contents of said modulus operand register generating an accumulator modulus product;
- and
- an adder that adds said accumulator modulus product with the contents of the additive operand register, and configured to send a least significant portion of the adder result to said digit accumulator, and a most significant portion of the result to a successive processing stage;
- and
- a second plurality of digit processing units that receive digit values and modulus values from said first plurality of digit processing units, and to perform one or more modular arithmetic operations on a plurality of residue digits, each digit processing unit comprising:
- a residue digit register that stores a residue digit;
- a modular multiplier that receives a modulus value from an input modulus bus and a value from said residue digit register, and is sends a residue product result;
- and
- a modular adder that receives said residue product result, and configured to receive a digit value from an input digit value bus;
- wherein after a plurality of processing cycles, a fractional residue number equivalent to a binary fractional input is stored in the plurality of said residue digit registers;
13 more elements
A method for multiplying a first fractional residue operand to a second fractional residue operand, comprising:
- separating a first fractional residue operand into a first fractional only portion and a first whole integer only portion;
- separating a second fractional residue operand into a second fractional only portion and a second whole integer only portion;
- multiplying the first fractional only portion with the second fractional only portion forming an intermediate fractional only product term;
- multiplying the first fractional only portion with the second whole integer only portion to form a first intermediate fraction and whole product term;
- multiplying the second fractional only portion with the first whole integer only portion to form a second intermediate fraction and whole product term;
- multiplying the first whole integer only portion with the second whole integer only portion forming a whole integer only product;
- scaling the whole integer only product by a fractional range value forming a scaled whole integer only product;
- truncating a first fractional only portion forming a truncated first fractional only portion;
- truncating a second fractional only portion forming a truncated second fractional only portion;
- multiplying the truncated first fractional only portion with the truncated second fractional only portion forming a truncated partial product;
- subtracting the truncated partial product from aforementioned intermediate fractional only product term forming an intermediate fractional product term evenly divisible by a fractional range;
- multiplying the intermediate fractional product term that is evenly divisible by a fractional range with a multiplicative inverse of a fractional range forming a recovered fractional only portion;
- wherein a final result is generated by summing a recovered fractional only portion, a first intermediate fraction and whole product term, a second intermediate fraction and whole product term, and a scaled whole integer only product.
10 more elements
Dependencies are inferred from the claim text.