Flexible architecture and instruction for advanced encryption standard (aes)

A system comprising:

• a memory controller to control communication with a double data rate memory;
• and
• a processor comprising:
• a plurality of cores;
• a level 1 instruction cache to cache instructions;
• a level 1 data cache;
• a bus interface unit;
• a plurality of 128-bit registers;
• a decode unit to decode the instructions from the level 1 instruction cache including four Advanced Encryption Standard (AES) instructions, wherein each of the four AES instructions has a unique opcode, the four AES instructions including:
• a first AES decryption instruction that is to use a 128-bit source/destination register of the plurality and a 128-bit source register of the plurality, and
• a second AES decryption instruction that is to use a 128-bit source register of the plurality and a 128-bit destination register of the plurality;
• and
• an execution unit coupled to the decode unit, such that:
• the first AES decryption instruction is to cause the execution unit to receive data from the 128-bit source/destination register and the 128-bit source register of the first AES decryption instruction, perform operations for an AES single decryption round including an inverse byte substitution, an inverse shift rows, and an exclusive OR, but omitting an inverse mix columns, and store a first result in the 128-bit source/destination register;
• and
• the second AES decryption instruction is to cause the execution unit to receive data from the 128-bit source register of the second AES decryption instruction, perform operations including an inverse mix columns, and store a second result in the 128-bit destination register of the second AES decryption instruction.

A system comprising:

• a memory controller to control communication with a memory;
• and
• a processor comprising:
• a plurality of cores;
• a level 1 instruction cache to cache instructions;
• a level 1 data cache;
• a bus interface unit;
• a plurality of 128-bit registers;
• a decode unit to decode the instructions from the level 1 instruction cache including four Advanced Encryption Standard (AES) instructions, wherein each of the four AES instructions has a unique opcode, the four AES instructions including:
• a first AES decryption instruction that is to use a 128-bit source/destination register of the plurality and a 128-bit source register of the plurality, and
• a second AES decryption instruction that is to use a 128-bit source register of the plurality and a 128-bit destination register of the plurality;
• and
• an execution unit coupled to the decode unit, such that:
• the first AES decryption instruction is to cause the execution unit to receive data from the 128-bit source/destination register and the 128-bit source register of the first AES decryption instruction, perform operations for an AES single decryption round including an inverse byte substitution, an inverse shift rows, and an exclusive OR, but omitting an inverse mix columns, and store a first result in the 128-bit source/destination register;
• and
• the second AES decryption instruction is to cause the execution unit to receive data from the 128-bit source register of the second AES decryption instruction, perform operations including an inverse mix columns, and store a second result in the 128-bit destination register of the second AES decryption instruction.