Partial Response Equalizer and Related Method

An integrated circuit receiver, comprising:

• first sampling circuitry to sample a first symbol carried by a signal over a signaling lane, wherein the first sampling circuitry includes
• at least two samplers to generate respective, conditional first symbol values in dependence on alternative, assumed logic states of a prior symbol carried by the signal, and
• circuitry to select one of the respective, conditional first symbol values dependent on a resolved logic state of the prior symbol;
• second sampling circuitry to sample a second symbol carried by the signal over the signaling lane, the second symbol following the first symbol, wherein the second sampling circuitry includes
• at least two samplers to generate respective, conditional second symbol values in dependence on alternative, assumed logic states of the first symbol, and
• circuitry to select one of the respective, conditional second symbol values in dependence on the selected one of the respective first symbol values;
• and
• a latch to sample an output of the circuitry to select one of the respective, conditional second symbol values according to a selected phase of a clock signal.

An integrated circuit receiver, comprising:

• first sampling circuitry to sample a first symbol carried by a first phase of a double-data rate signal, the first sampling circuitry to generate conditional values of the first symbol in dependence on respective, possible values of an immediately prior symbol carried by a second phase of the signal, and to select one of the conditional values of the first symbol dependent on a resolved value of the immediately prior symbol;
• second sampling circuitry to sample a second symbol carried by the second phase of the double-data rate signal, the second symbol immediately following the first symbol, the second sampling circuitry to generate conditional values of the second symbol in dependence on possible values of the first symbol, and to select one of the conditional values of the second symbol in dependence on a resolved value for the first symbol;
• a first latch to sample an output of the second sampling circuitry according to a selected phase of a clock signal and to output a resolved value of the second symbol;
• and
• a second latch to sample an output of the first sampling circuitry according to the selected phase and to output a resolved value of the first symbol.