Configurable delay circuit and method of clock buffering

A method of clock buffering, comprising:

• selecting a delay path having a configurable delay formed by a plurality of transistor stacks serially electrically couplable by respective delay path select circuits;
• and
• employing said respective delay path select circuits in electrically coupling said plurality to a base delay path, thereby activating said delay path and allowing a clock signal to propagate therein.

A static random access memory (SRAM) clock circuit, comprising:

• a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered;
• and
• a delay path select circuit respectively electrically coupled between pairs of said plurality of transistor stacks and operable to selectively electrically couple said plurality of transistor stacks to a base delay path, thereby activating said configurable delay path based on a desired delay.