Memory device, method of controlling memory device, and memory system

A method of controlling a memory device, the memory device comprising:

• in the case that three directions intersecting each other are assumed to be an X direction, a Y direction, and a Z direction,
• a memory cell array including:
• row lines that are aligned in a two-dimensional array shape in the Y direction and the Z direction and extend in the X direction;
• column lines that are aligned in a two-dimensional array shape in the X direction and the Y direction and extend in the Z direction;
• a plurality of global bit lines that are aligned in the X direction and extend in the Y direction;
• selection elements that are provided at ends of the column lines;
• and cells that are provided between the row lines and the column lines;
• a selection circuit including:
• a row line selection circuit being configured to select at least one selected row line from the row lines;
• a global bit line selection circuit being configured to select at least one selected global bit line from the global bit lines;
• and a selection element control circuit being configured to control the selection elements to connect/disconnect between the selected global bit line and one of the column lines;
• and
• a data processing circuit,
• the method comprising the following steps executed by the data processing circuit, namely the steps of:
• during write and read of data to/from the cell,
• processing input data to generate first intermediate data;
• sequentially setting a voltage difference between the selected row line and the selected global bit line based on the first intermediate data;
• detecting a current flowing in the selected global bit line and sequentially generating second intermediate data from a result of that detection;
• processing the second intermediate data to generate output data;
• and
• when processing the input data to generate the first intermediate data and when processing the second intermediate data to generate the output data, correcting a difference that may occur between the input data and the output data.

A memory system, comprising:

• a memory main body chip that includes:
• in the case that three directions intersecting each other are assumed to be an X direction, a Y direction, and a Z direction,
• a memory cell array including:
• a plurality of row lines that are aligned in a two-dimensional array shape in the Y direction and the Z direction and extend in the X direction;
• a plurality of column lines that are aligned in a two-dimensional array shape in the X direction and the Y direction and extend in the Z direction;
• a plurality of global bit lines that are aligned in the X direction and extend in the Y direction;
• a plurality of selection elements that are provided at each of ends of the plurality of column lines and electrically connect/disconnect a plurality of the column lines aligned in the Y direction and a certain one of the global bit lines;
• and a plurality of cells that are provided at each of intersections of the plurality of row lines and the plurality of column lines,
• a selection circuit including:
• a row line selection circuit that selects a certain row line from the plurality of row lines;
• a global bit line selection circuit that selects a certain global bit line from the plurality of global bit lines;
• and a selection element control circuit that controls connection/disconnection of the global bit line and the column line by the plurality of selection elements, and
• a second data processing circuit that performs write and read of data to/from the cell;
• and
• a controller chip comprising a first data processing circuit that performs write and read of data to/from the cell,
• the first data processing circuit of the controller chip including a first data write pre-processing circuit that processes input data to generate third intermediate data,
• the second data processing circuit of the memory main body chip including:
• a second data write pre-processing circuit that processes the third intermediate data to generate first intermediate data;
• a data write processing circuit that sequentially sets a voltage difference between the selected row line and the selected global bit line based on the first intermediate data;
• a data read processing circuit that detects a current flowing in the selected global bit line and sequentially generates second intermediate data from a result of that detection;
• and
• a second data read post-processing circuit that processes the second intermediate data to generate fourth intermediate data,
• the first data processing circuit of the controller chip further including a first data read post-processing circuit that processes the fourth intermediate data to generate output data, and
• the first and second data write pre-processing circuits and the first and second data read post-processing circuits having a correcting function that corrects a difference that may occur between the input data and the output data.