Memory device, writing method, and reading method

A method for writing information with respect to a memory device which is provided with a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, where the storage section is provided with a plurality of memory elements which are able to be written one time and where information is held by changing resistance values in a non-written state and a written state, the method comprising:

• applying a predetermined potential difference or more to both ends of one memory element in the storage section of the memory cell which is the writing target by controlling the cell selection section of the memory cell which is a writing target to be in an on state using a word line which corresponds to the memory cell which is the writing target out of a plurality of word lines which are arranged with respect to a memory cell array where the memory cells are arranged in a shape of a matrix and applying a voltage using a bit line which corresponds to the memory cell which is the writing target out of a plurality of bit lines which are arranged with respect to the memory cell array, and
• writing to the one memory element.

A method for reading information with respect to a memory device which is provided with a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, where the storage section is provided with a plurality of memory elements which are able to be written one time and where information is held by changing resistance values in a non-written state and a written state, the method comprising:

• reading information which is stored in the memory elements in the storage section by detecting a composite resistance value of the cell selection section and the storage section by controlling the cell selection section of the memory cell which is a reading target to be an on state using a word line which corresponds to the memory cell which is the reading target out of a plurality of word lines which are arranged with respect to a memory cell array where the memory cells are arranged in a shape of a matrix, and applying a voltage to the cell selection section of the memory cell which is the reading target and the storage section using bit lines which correspond to the memory cell which is the reading target out of a plurality of bit lines which are arranged with respect to the memory cell array.