Supporting atomic operations as post-synchronization operations in graphics processing architectures
AssigneeIntel Corporation
InventorsHema C. Nalluri, Aditya Navale, Altug Koker
Life of this patent
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Abstract
Methods and systems may provide for storing a set of post-synchronization operations to a graphics memory and sending a flush marker to a graphics pipeline. Additionally, the set of post-synchronization operations may be processed in response to the flush marker exiting the graphics pipeline. In one example, the set of post-synchronization operations includes one or more atomic operations. Moreover, the set of post-synchronization operations may be obtained from an inline portion of an atomics command.
Claims25
A system comprising:
- a display to present visual content;
- a host processor to execute a driver, the driver to issue a set of post-synchronization operations associated with the visual content;
- a graphics memory;
- and
- a graphics processor including,
- a memory module to store the set of post-synchronization operations to the graphics memory,
- a pipeline module to send a flush marker to a graphics pipeline, and
- an execution module to process the set of post-synchronization operations in response to the flush marker exiting the graphics pipeline.
A method comprising:
- storing a set of post-synchronization operations to a graphics memory;
- sending a flush marker to a graphics pipeline;
- and
- processing the set of post-synchronization operations in response to the flush marker exiting the graphics pipeline.
At least one computer readable storage medium comprising a set of instructions which, if executed by a computing device, cause the computing device to:
- store a set of post-synchronization operations to a graphics memory;
- send a flush marker to a graphics pipeline;
- and
- process the set of post-synchronization operations in response to the flush marker exiting the graphics pipeline.
An apparatus comprising:
- a memory module to store a set of post-synchronization operations to a graphics memory;
- a pipeline module to send a flush marker to a graphics pipeline;
- and
- an execution module to process the set of post-synchronization operations in response to the flush marker exiting the graphics pipeline.
Dependencies are inferred from the claim text.