Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same

A method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device, comprising:

• performing a semiconductor substrate, having a first conductivity type;
• forming an epitaxial semiconductor layer over the semiconductor substrate, having the first conductivity type;
• forming a first doped region in a portion of the epitaxial semiconductor layer, having a second conductivity type opposite to the first conductivity type;
• forming a first dielectric layer over the first doped region in the epitaxial semiconductor layer;
• forming a second dielectric layer over a portion of the epitaxial semiconductor layer, being adjacent to the first dielectric layer and in contacting therewith, wherein the first dielectric layer and the second dielectric layer have different thicknesses;
• forming a gate stack over a portion of the first dielectric layer and a portion of the second dielectric layer;
• forming a second doped region in a portion of the epitaxial semiconductor layer adjacent to a first side of the gate stack, having the first conductivity type;
• forming a third doped region in a portion of the second doped region at the first side of the gate stack, having the second conductivity type opposite to the first conductivity type;
• forming an insulating layer over the first dielectric layer, the gate stack, and the second dielectric layer;
• forming a first trench at the first side of the gate stack, wherein the first trench penetrates a portion of the insulating layer, the second dielectric layer, the third doped region, the first doped region, and the epitaxial semiconductor layer;
• performing a first ion implantation process, forming a fourth doped region in a portion of the epitaxial semiconductor layer exposed by the first trench, wherein the fourth doping region contacts the semiconductor substrate and has the first conductivity type;
• forming a first conductive contact in the first trench, contacting the fourth doped region;
• forming an interlayer dielectric layer over the insulating layer and the first conductive contact;
• forming a second trench at the second side of the gate stack opposite to the first side, wherein the second trench penetrates a portion of the interlayer dielectric layer, the insulating layer, and the second dielectric layer and exposes a portion of the first doped region;
• performing a second ion implantation process, forming a fifth doped region in a portion of the first doped region exposed by the second trench, wherein the fifth doped region has the second conductivity type;
• and
• forming a second conductive contact in the second trench, contacting the fifth doped region.