Two-Transistor Non-Volatile Memory Cell and Related Program and Read Methods
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTe-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
Life of this patent
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Abstract
A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
Claims20
A structure comprising:
- a substrate;
- a first transistor having a first drain, a first source, and a first channel region extending between the first drain and the first source;
- a second transistor having a second drain, a second source, and a second channel region extending between the first drain and the first source;
- a floating gate electrode extending over both the first channel region and the second channel region;
- a first connection electrically connecting the first drain and a word line;
- a second connection electrically connecting the second source and the word line;
- a third connection electrically connecting the first source and a first bit line;
- and
- a fourth connection electrically connecting the second drain and a second bit line.
A memory array comprising:
- a first memory cell, the first memory cell including
- a first transistor and a second transistor, the first and second transistor sharing a common floating gate,
- a common word line electrically connected to a drain of the first transistor and a source of the second transistor,
- a first bit line connected to a source of the first transistor, and
- a second bit line connected to a drain of the second transistor, and a second memory cell, the second memory cell including
- a third transistor and a fourth transistor, the third and fourth transistor sharing a second common floating gate,
- the common word line electrically connected to a drain of the third transistor and a source of the fourth transistor,
- a third bit line connected to a source of the third transistor, and
- a fourth bit line connected to a drain of the fourth transistor.
An integrated circuit comprising:
- a processor configured to performed programmed functions;
- and
- a programmable non-volatile memory array organized into rows and columns, each memory cell in a row sharing a common word line and each memory cell in a column sharing a first common bit line and a second common bit line, each memory cell further including:
- a first transistor and a second transistor, the first and second transistor sharing a common floating gate,
- a first electrical path between the common word line electrically, a drain of the first transistor, and a source of the second transistor,
- a second electrical path between the first common bit line and a source of the first transistor, and
- a third electrical path between the second bit line and a drain of the second transistor.
Dependencies are inferred from the claim text.