Ultralow power carbon nanotube logic circuits and method of making same

A complementary metal-oxide-semiconductor (CMOS) logic device formed with carbon nanotubes (CNTs), comprising:

• at least one p-type metal-oxide-semiconductor (PMOS) transistor formed with the CNTs, wherein each of the at least one PMOS transistor has a gate, a source and a drain;
• and
• at least one n-type metal-oxide-semiconductor (NMOS) transistor formed with the CNTs, wherein each of the at least one NMOS transistor has a gate, a source and a drain,
• wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage;
• wherein at least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage VOUT;
• wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor respectively comprises a local metallic gate structure formed of a metal.

A method of fabricating a complementary metal-oxide-semiconductor (CMOS) logic device with single-walled carbon nanotubes (SWCNTs), comprising:

• forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate;
• forming a plurality of contacts on the substrate;
• and
• depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one n-type metal-oxide-semiconductor (NMOS) transistor and at least one p-type metal-oxide semiconductor (PMOS) transistor, wherein each of the at least one NMOS transistor and each of the at least one PMOS transistor has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively;
• wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage;
• and
• wherein at least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage VOUT.