Semiconductor memory device having three-dimensional cross point array

A semiconductor memory device comprising:

• a substrate;
• pillars extending upright on the substrate in a direction perpendicular to a major surface of the substrate;
• an insulating layer extending along the sides of the pillars;
• a semiconductor layer on the insulating layer;
• an interlayer insulating layer pattern and a first conductive layer pattern disposed in a stack on the substrate, wherein the stack extends vertically alongside the pillars;
• a second conductive layer pattern interposed between the pillars and the first conductive layer pattern;
• and
• a variable resistance layer interposed between the first conductive layer pattern and the second conductive layer pattern.

A semiconductor memory device comprising:

• a first word line;
• a first local bit line including a first transistor and a second transistor that are connected to each other in series;
• a first virtual bit line connecting gates of the first transistor and the second transistor;
• and
• a first variable resistance memory cell connected in the device between the first word line and a common node where the first transistor and the second transistor are connected to each other in series.