Operation of a dual instruction pipe virus co-processor

A system comprising:

• a system memory;
• a general purpose processor, wherein the general purpose processor is communicably coupled to the system memory, and wherein the general purpose processor is operable to store a data segment to the system memory;
• a virus co-processor operable to access the data segment from the system memory, wherein the virus co-processor includes at least a first instruction pipe and a second instruction pipe, wherein the first instruction pipe is operable to execute a first instruction type, and wherein the second instruction pipe is operable to execute a second instruction type;
• and
• a computer readable medium, wherein the computer readable medium includes at least one virus signature, wherein the at least one virus signature includes a first instruction of the first instruction type and a second instruction of the second instruction type, and wherein the first instruction and the second instruction are maintained on the computer readable medium;
• and
• wherein the first instruction pipe includes a first write back circuit, wherein the second instruction pipe includes a second write back circuit, and wherein the first write back circuit and the second write back circuit are linked such that a write back of a preceding instruction occurs before a write back of a succeeding instruction.

A system comprising:

• a system memory;
• a general purpose processor, wherein the general purpose processor is communicably coupled to the system memory, and wherein the general purpose processor is operable to store a data segment to the system memory;
• a virus co-processor, wherein the virus co-processor is communicably coupled to the system memory, and wherein the virus co-processor is operable to retrieve the data segment from the system memory;
• an instruction memory, wherein the instruction memory is communicably coupled to the virus co-processor, and wherein the instruction memory includes at least one virus signature, wherein the at least one virus signature includes a first instruction of a first instruction type and a second instruction of a second instruction type, and wherein the first instruction and the second instruction are maintained on the computer readable medium at contiguous locations;
• wherein the virus co-processor includes at least a first instruction pipe and a second instruction pipe, the first instruction pipe is operable to execute the first instruction type, and the second instruction pipe is operable to execute the second instruction type;
• and
• wherein the first instruction pipe includes a first write back circuit, wherein the second instruction pipe includes a second write back circuit, and wherein the first write back circuit and the second write back circuit are linked such that a write back of a preceding instruction occurs before a write back of a succeeding instruction.