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US 2015/0092636 A1Published application
Single local oscillator architecture
OwnerAhmadreza Rofougaran, Maryam Rofougaran +1inventors
InventorsAhmadreza Rofougaran, Maryam Rofougaran, Alireza Zolfaghari
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Abstract
A system and method in a transceiver for reducing power. In transmission mode (Tx), a local oscillator (LO) generator (LOGEN) circuit modifies a PLL oscillation signal that runs at a fraction of the carrier signal. In the receive mode (Rx), the LOGEN circuit increases power consumption unnecessarily and is bypassed in favor of a PLL output which is a multiple of the carrier signal.
Claims20
A transceiver comprising:
- a receiver processing chain including at least a down-converter;
- a transmission processing chain including at least an up-converter;
- a phase lock loop coupled to both the down-converter and the up-converter;
- and
- wherein the phase lock loop is configured, in a receive mode, to generate a first output oscillation signal at a multiple of a carrier frequency and, in a transmit mode, to generate a second output oscillation signal at a fraction of the carrier frequency.
2 more elements
A transceiver comprising:
- a receiver processing chain including at least a down-converter;
- a first transmission processing chain generating a constant envelope transmission signal;
- a second transmission processing chain including at least an up-converter and generating a variable envelope;
- a phase lock loop coupled to the receiver and first and second transmission processing chains;
- and
- wherein the phase lock loop is configured in:
- a receive mode to generate a first output oscillation signal at a multiple of a carrier frequency;
- a first transmit mode to generate the constant envelope using the multiple of the carrier frequency;
- and a second transmit mode generating the variable envelope using a second output oscillation signal at a fraction of the carrier frequency.
6 more elements
A frequency-division duplex transceiver comprising:
- a duplexer for receiving bi-directional communication signals including a receive signal and transmit signal;
- a receiver processing chain including at least a down-converter;
- a transmission processing chain including at least an up-converter;
- a phase lock loop shared by the receiver and transmission processing chains, the phase lock loop configured to generate an output oscillation signal at a multiple of the carrier frequency;
- a digital signal processor;
- and
- wherein the transceiver is configured to down-convert the receive signal to an intermediate frequency followed by the digital signal processor digitally down-converting the intermediate frequency and up-convert the transmit signal.
4 more elements
Dependencies are inferred from the claim text.