Dual port sram with dummy read recovery

An integrated circuit, comprising:

• a first port word line;
• a second port word line;
• a first port bit line and a first port complementary bit line;
• a second port bit line and a second port complementary bit line;
• a dual port SRAM cell having a data node coupled to the first and second port bit lines under control of the first and second port word lines and a complementary data node coupled to the first and second port complementary bit lines under control of the first and second port word lines;
• and
• a dummy read recovery block configured to couple the second port complementary bit line to a high voltage supply node during a write logic low operation to the data node of the SRAM cell through the first port bit line, and to couple the second port bit line to a high voltage supply node during a write logic low operation to the complementary data node of the SRAM cell through the first port complementary bit line, wherein only one of the second port bit line and second port complementary bit line is coupled to the high voltage supply node during a given write logic low operation.

A method of writing data to a dual port SRAM memory cell of an integrated circuit, the SRAM memory cell having a data node coupled to first and second port bit lines under control of first and second port word lines and a complementary data node coupled to first and second port complementary bit lines under control of first and second port word lines comprising, the method comprising the steps of:

• enabling both the first and second port word lines;
• writing a low voltage to the data node and a high voltage to the complementary data node through the first port bit line and first port complementary bit line, respectively;
• and
• during the writing step, coupling only the second port complementary bit line from the second port bit line and second port complementary bit line to a high voltage supply node.