System and method to trim reference levels in a resistive memory

An apparatus comprising:

• a resistive memory reference array comprising multiple sets of reference cells;
• a reference resistance measurement circuit, wherein a first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells, and wherein a second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells;
• and
• a trimming circuit configured to set a reference resistance based on an average effective reference resistance of a plurality of effective reference resistances, wherein the plurality of effective reference resistances includes the first effective reference resistance and the second effective reference resistance.

An apparatus comprising:

• a semiconductor device comprising:
• means for storing multiple reference resistance values, the multiple reference resistance values arranged in multiple sets of reference cells;
• means for accessing a first set of reference cells to measure a first effective reference resistance corresponding to the first set of reference cells and accessing a second set of reference cells to measure a second effective reference resistance corresponding to the second set of reference cells;
• and
• means for setting a reference resistance based on an average effective reference resistance of a plurality of effective reference resistances, wherein the plurality of effective reference resistances includes the first effective reference resistance and the second effective reference resistance.

A method comprising:

• a first step for initiating, at a resistive memory device, measuring of a first effective reference resistance, the first effective reference resistance based on a first set of reference cells of the resistive memory device;
• a second step for initiating, at the resistive memory device, measuring of a second effective reference resistance, the second effective reference resistance based on a second set of reference cells of the resistive memory device;
• a third step for initiating, at the resistive memory device, determining of a target reference resistance level based on an average effective reference resistance of a plurality of effective reference resistances, wherein the plurality of effective reference resistances includes the first effective reference resistance and the second effective reference resistance;
• and
• a fourth step for initiating, at the resistive memory device, trimming of a reference resistance at least partially based on the target reference resistance level.

A computer readable storage device storing instructions that, when executed by a processor, cause the processor to perform operations comprising:

• at resistive memory device:
• initiating measuring of a first effective reference resistance, the first effective reference resistance based on a first set of reference cells of the resistive memory device;
• initiating measuring of a second effective reference resistance, the second effective reference resistance based on a second set of reference cells of the resistive memory device;
• initiating determining of a target reference resistance level based on an average effective reference resistance of a plurality of effective reference resistances, wherein the plurality of effective reference resistances includes the first effective reference resistance and the second effective reference resistance;
• and
• initiating trimming of a reference resistance at least partially based on the target reference resistance level.

A method comprising:

• receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising:
• a resistive memory reference array comprising multiple sets of reference cells;
• a reference resistance measurement circuit, wherein a first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells, and wherein a second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells;
• and
• a trimming circuit configured to set a reference resistance of the resistive memory reference array based on an average effective reference resistance of a plurality of effective reference resistances, wherein the plurality of effective reference resistances includes the first effective reference resistance and the second effective reference resistance;
• and
• transforming the design information to comply with a file format;
• and
• generating a data file including the transformed design information.

A method comprising:

• receiving a data file comprising design information corresponding to a semiconductor device;
• and
• fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
• a resistive memory reference array comprising multiple sets of reference cells;
• a reference resistance measurement circuit, wherein a first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells, and wherein a second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells;
• and
• a trimming circuit configured to set a reference resistance of the resistive memory reference array based on an average effective reference resistance of a plurality of effective reference resistances, wherein the plurality of effective reference resistances includes the first effective reference resistance and the second effective reference resistance.

A method comprising:

• receiving design information comprising physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device comprising:
• a resistive memory reference array comprising multiple sets of reference cells;
• a reference resistance measurement circuit, wherein a first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells, and wherein a second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells;
• and
• a trimming circuit configured to set a reference resistance of the resistive memory reference array based on an average effective reference resistance of a plurality of effective reference resistances, wherein the plurality of effective reference resistances includes the first effective reference resistance and the second effective reference resistance;
• and
• transforming the design information to generate a data file.

A method comprising:

• receiving a data file comprising design information comprising physical positioning information of a packaged semiconductor device on a circuit board;
• and
• manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises:
• a resistive memory reference array comprising multiple sets of reference cells;
• a reference resistance measurement circuit, wherein a first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells, and wherein a second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells;
• and
• a trimming circuit configured to set a reference resistance of the resistive memory reference array based on an average effective reference resistance of a plurality of effective reference resistances, wherein the plurality of effective reference resistances includes the first effective reference resistance and the second effective reference resistance.