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US 2015/0091919 A1Published application
Sampler load balancing
AssigneeIntel Corporation
InventorsHema Chand Nalluri, Joy Chandra, Prosun Chatterjee, Benjamin Pletcher, Yoav Harel, Steven Spangler
Life of this patent
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Abstract
Embodiments described herein include a graphics processing unit. The graphics processing unit includes a plurality of execution units. The graphics processing unit also includes a plurality of sampler units. Each sampler unit corresponds to a sampler dispatch logic unit and at least one execution unit, and the sampler dispatch logic units are used to network the plurality of sampler units.
Claims24
A graphics processing unit, comprising:
- a plurality of execution units;
- and
- a plurality of sampler units, each sampler unit corresponding to a sampler dispatch logic unit and at least one execution unit, wherein the sampler dispatch logic units are used to network the plurality of sampler units.
A method for sampler load balancing, comprising:
- receiving a sample instruction at an execution unit;
- and
- routing the sample instruction from the execution unit to a sampler unit based on a sampler dispatch logic, wherein the sampler dispatch logic forms a network that includes a plurality of sampler units.
A system that includes a sampler dispatch logic, comprising:
- a display;
- a radio;
- a memory that is to store instructions and that is communicatively coupled to the display;
- and
- a processor communicatively coupled to the radio and the memory, wherein when the processor is to execute the instructions, the processor is to:
- receive a sample instruction at an execution unit;
- and
- route the sample instruction from the execution unit to a sampler unit based on a sampler dispatch logic, wherein the sampler dispatch logic forms a network that includes a plurality of sampler units.
5 more elements
Dependencies are inferred from the claim text.