Semiconductor testing jig and transfer jig for the same

A semiconductor testing jig for testing a plurality of vertical semiconductor devices each having a lower surface electrode and an upper surface electrode, said semiconductor testing jig comprising:

• a conductive stage including a plurality of mounting portions on which said plurality of vertical semiconductor devices are each individually disposed with said lower surface electrodes being in contact with said plurality of mounting portions;
• an insulating frame portion having a lattice pattern that is disposed on said stage and surrounds each of said plurality of mounting portions in plan view to define each of said mounting portions;
• and
• an abrasive layer disposed in a position in said frame portion, said position facing each of said vertical semiconductor devices disposed on said mounting portions.