Chip Embedded Package Method and Structure

A chip embedded package method applied to at least two organic substrates, wherein, each organic substrate comprises:

• a core layer sandwiched between two metal layers;
• the two metal layers, one metal layer is thicker than the other one, and the method comprises:
• etching metallic sinks on the thicker metal layer of each organic substrate;
• part of metallic sinks are used for packaging at least one chip, and other metallic sinks are used for via-holes;
• mounting the at least one chip into a metallic sink of each organic substrate via adhesive;
• flipping one organic substrate on another to form a combination;
• drilling blind-holes on both sides of the combination of the two organic substrates to pass through the adhesive;
• drilling via-holes to get through the combination of the two organic substrates, wherein the via-holes locates beyond the metallic sinks with chips;
• filling the blind-holes and via-holes with conductive medium through an electroplating process.