Vertical noise reduction in 3d stacked semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShu-Chun Yang
Life of this patent
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Abstract
A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 μm. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.
Claims20
A stacked three dimensional semiconductor device comprising:
- a plurality of tiers stacked over one another, each including a substrate and a layer of insulating material formed thereover, said plurality of tiers including active tiers and noise suppression tiers, said active tiers including active semiconductor devices and said noise suppression tiers including a power/ground mesh and decoupling capacitors and no active semiconductor devices that generate electrical noise in functional operation,
- wherein at least one said noise suppression tier is vertically interposed between two of said active tiers and said power/ground mesh is connected to circuitry of said active devices formed on said active tiers.
A stacked 3D semiconductor device comprising:
- a plurality of tiers stacked over one another, each including a substrate and a layer of insulating material thereover, each said substrate including at least one active device portion with active devices thereon and at least one noise suppression portion with decoupling capacitors and a power/ground mesh thereon and no active devices that generate electrical noise in functional operation, thereon,
- wherein said tiers are stacked over one another such that at least one said noise suppression portion of one said substrate is vertically interposed between active portions of subjacent and superjacent ones of said substrates.
A stacked 3D semiconductor device comprising:
- a plurality of tiers stacked over one another, each including a semiconductor substrate and a layer of insulating material thereover, each said semiconductor substrate including at least one active device portion with active devices thereon and at least one noise suppression portion with decoupling capacitors and a power/ground mesh thereon and no active devices that generate electrical noise in functional operation, thereon,
- said tiers stacked over one another such that at least one said noise suppression portion of one said substrate is vertically interposed between active portions of subjacent and superjacent ones of said substrates, said semiconductor substrates having a thickness less than about 0.2 μm, and at least some of said decoupling capacitors coupled between ground and a power line.
Dependencies are inferred from the claim text.