Non-volatile memory (nvm) and high-k and metal gate integration using gate-first methodology

A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion and a logic portion, comprising:

• growing thermal oxide on the substrate in the NVM portion;
• forming a select gate in the NVM portion on the thermal oxide;
• counterdoping the substrate in the NVM portion adjacent to the select gate;
• forming a control gate and a charge storage layer over the substrate in the NVM portion, wherein a top surface of the control gate is substantially coplanar with a top surface of the select gate and the charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, is partially over the top surface of the select gate;
• forming a protective layer over the NVM portion and the logic portion;
• removing the protective layer from the logic portion;
• forming a gate structure in the logic portion comprising a high k dielectric as a gate dielectric and a metal gate over the gate dielectric that sets a work function;
• depositing a dielectric layer over the NVM portion and the logic portion;
• performing an etch of the dielectric layer to form a first sidewall spacer around the select gate and the control gate, and a second sidewall spacer around the metal gate;
• and
• performing an implant into the substrate using the first and second sidewall spacers.

A semiconductor structure using a substrate having a non-volatile memory (NVM) portion and a logic portion, comprising:

• a select gate comprising polysilicon over a thermal oxide layer on the substrate in the NVM portion;
• a control gate adjacent a first side of the select gate and having a top surface substantially coplanar with a top surface of the select gate;
• a charge storage layer (,) having a first portion between the control gate and the substrate, a second portion between the control gate and the first side of the select gate, and a third portion partially over the select gate;
• and
• a logic gate comprising metal over a high k dielectric over the substrate in the logic portion.