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US 2015/0091056 A1Published application
Semiconductor device for electrostatic discharge protection
AssigneeSofics BVBA
InventorsBart Sorgeloos, Benjamin Van Camp, Olivier Marichal
Life of this patent
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Abstract
Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.
Claims20
An ESD protection circuit, comprising:
- a lowly doped P region;
- a lowly doped N region formed in the first lowly doped P region;
- a first highly doped P region formed entirely within the lowly doped P region;
- a second highly doped N region formed entirely within the lowly doped P region;
- a third highly doped P region formed entirely within the lowly doped N region;
- a fourth highly doped N region formed entirely within the lowly doped N region;
- a fifth highly doped N region formed entirely within the lowly doped P region, wherein the fifth highly doped N region is coupled to the third highly doped P region;
- and
- a trigger circuit coupled to at least one of the first highly doped P region and the fourth highly doped N region;
- wherein:
- the lowly doped N region, the lowly doped P region, and the second highly doped N region form an NPN transistor;
- the third highly doped P region, the lowly doped N region, and the lowly doped P form a PNP transistor;
- the NPN transistor and PNP transistor form a silicon controller rectifier (SCR);
- and
- the fifth highly doped N region provides additional carriers to facilitate triggering of the SCR during an ESD event.
12 more elements
An ESD protection circuit, comprising:
- a lowly doped P region;
- a lowly doped N region formed in the first lowly doped P region;
- a first highly doped P region formed entirely within the lowly doped P region;
- a second highly doped N region formed entirely within the lowly doped P region;
- a third highly doped P region formed entirely within the lowly doped N region;
- a fourth highly doped N region formed entirely within the lowly doped N region;
- a fifth highly doped P region formed entirely within the lowly doped N region, wherein the fifth highly doped N region is coupled to the second highly doped N region;
- and
- a trigger circuit coupled to at least one of the first highly doped P region and the fourth highly doped N region;
- wherein:
- the lowly doped N region, the lowly doped P region, and the second highly doped N region form an NPN transistor;
- the third highly doped P region, the lowly doped N region, and the lowly doped P form a PNP transistor;
- the NPN transistor and PNP transistor form a silicon controller rectifier (SCR);
- and
- the fifth highly doped P region provides additional carriers to facilitate triggering of the SCR during an ESD event.
12 more elements
Dependencies are inferred from the claim text.