Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same

A system on chip (SoC) comprising:

• a CPU;
• a graphics processing unit (GPU);
• a clock generator configured to generate a reference clock signal;
• a clock controller configured to,
• detect a change in an operating state of at least one of the CPU and the GPU,
• generate an operating clock signal based on the reference clock signal, and
• change an operating frequency of the at least one of the CPU and the GPU in response to the detected change;
• a display controller configured to control an operation of a display device;
• a read only memory (ROM);
• a random access memory (RAM);
• and
• a memory controller configured to control an external memory device,
• wherein the operating frequency of the at least one of the CPU and the GPU is greater than zero, and
• wherein the operating state of the at least one of the CPU and the GPU includes an active state, an idle state and a wakeup state.

A system on chip (SoC) comprising:

• a multi-core processor including a first core and a second core;
• a clock generator configured to generate a reference clock signal;
• a clock controller configured to,
• detect a change in an operating state of the first core and an operating state of the second core,
• generate operating clock signals based on the reference clock signal,
• change an operating frequency of the first core in response to the detected change in the operating state of the first core, and
• change an operating frequency of the second core in response to the detected change in the operating state of the second core;
• a display controller configured to control an operation of a display device;
• and
• a memory controller configured to control an external memory device, wherein
• the operating frequency of the first core is greater than zero,
• the operating frequency of the second core is greater than zero,
• the operating state of the first core includes an active state, an idle state and a wakeup state,
• the operating state of the second core includes an active state, an idle state and a wakeup state,
• the operating clock signals include a first operating clock signal and a second operating clock signal,
• the first core is configured to receive the first operating clock signal, and
• the second core is configured to receive the second operating clock signal.

A portable electronic system comprising:

• an image sensor;
• a memory;
• a display;
• and
• a system on chip (SoC) including
• a power management unit,
• a multi-core processor including a first core and a second core,
• a clock generator configured to generate a reference clock signal, and
• a clock controller configured to
• detect a change in an operating state of the first core and an operating state of the second core,
• generate operating clock signals based on the reference clock signal,
• change an operating frequency of the first core in response to the detected change in the operating state of the first core, and
• change an operating frequency of the second core in response to the detected change in the operating state of the second core,
• wherein the operating frequency of the first core is greater than zero,
• wherein the operating frequency of the second core is greater than zero,
• wherein the operating state of the first core includes an active state, an idle state and a wakeup state,
• wherein the operating state of the second core includes an active state, an idle state and a wakeup state,
• wherein the operating clock signals include a first operating clock signal and a second operating clock signal,
• wherein the first core is configured to receive the first operating clock signal,
• wherein the second core is configured to receive the second operating clock signal,
• wherein the clock controller is configured to increase the operating frequency of the first core when the operating state of the first core changes from the idle state to either the wakeup state or the active state,
• wherein the clock controller is configured to increase the operating frequency of the second core when the operating state of the second core changes from the idle state to either the wakeup state or the active state,
• wherein the clock controller is configured to decrease the operating frequency of the first core when the operating state of the first core changes from the active state to the idle state, and
• wherein the clock controller is configured to decrease the operating frequency of the second core when the operating state of the second core changes from the active state to the idle state.