SONOS FPGA Architecture Having Fast Data Erase and Disable Feature
AssigneeMicrosemi SoC Corporation
InventorJohn McCollum
Life of this patent
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Abstract
A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.
Claims20
An FPGA integrated circuit comprising:
- a programmable logic core;
- a controller;
- a configuration memory array including a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, driving a switch transistor coupled to one of a programmable logic element and a programmable interconnect connection of the programmable logic core;
- and
- a tamper detector disposed in the integrated circuit having an output coupled to the controller, the controller configured to cause power to be disconnected from the programmable logic core and to then simultaneously program all of the n-channel SONOS memory transistors and erase all of the p-channel SONOS memory transistors in the configuration memory array in response to a tamper detection signal from the tamper detector.
An FPGA integrated circuit comprising:
- a programmable logic core;
- a controller;
- a configuration memory array including a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, driving a switch transistor coupled to one of a programmable logic element and a programmable interconnect connection of the programmable logic core;
- a tamper detector disposed in the integrated circuit having an output coupled to the controller;
- and
- a power control switch disposed between the logic core and one of a source of supply voltage for the logic core and a ground connection for the logic core, the power control switch responsive to the controller for connecting and disconnecting power from the programmable logic core;
- the controller configured to disconnect power from the programmable logic core via the power control switch and then simultaneously program all of the n-channel SONOS memory transistors and erase all of the p-channel SONOS memory transistors in the configuration memory array in response to a tamper detection signal from the tamper detector.
A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, the method comprising:
- detecting tampering with the FPGA;
- disconnecting power from the programmable logic core;
- and
- simultaneously programming the n-channel SONOS memory transistors in the SONOS configuration memory cells and erasing the p-channel SONOS memory transistors in the SONOS configuration memory cells.
Dependencies are inferred from the claim text.