No-lead semiconductor package and method of manufacturing the same
AssigneeStmicroelectronics Pte Ltd
InventorsYiyi Ma, Kim-Yong Goh, Xueren Zhang
Life of this patent
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Abstract
A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed.
Claims19
A semiconductor package comprising:
- a die attach pad;
- a semiconductor die on the die attached pad, the semiconductor die including an active surface with a plurality of pads;
- a plurality of terminal leads;
- an encapsulant that encapsulates the semiconductor die and portions of side surfaces of the terminal leads;
- and
- a redistribution layer over the encapsulant, the redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads.
A method of manufacturing a semiconductor package, the method comprising:
- attaching a semiconductor die to a die attached pad of a conductive layer, the conductive layer further including a plurality of terminal leads proximate at least one side of the die attach pad, the semiconductor die having an active surface that includes a plurality of pads;
- encapsulating side surfaces of the semiconductor die and first portions of side surfaces of the terminal leads with an encapsulant;
- and
- electrically connecting the pads to the terminal leads via interconnections of a redistribution layer.
A semiconductor package comprising:
- a die attach pad having a first surface;
- a semiconductor die secured to the first surface of the die attached pad, the semiconductor die including an active surface with a plurality of pads;
- a plurality of terminal leads proximate at least one side of the die attach pad;
- an encapsulant along side surfaces of the semiconductor die and a portion of side surfaces of the terminal leads, the encapsulant, the semiconductor die, and the terminal leads forming a substantially planar surface;
- and
- a redistribution layer located on the substantially planar surface, the redistribution layer including a plurality of interconnections, each of the interconnections electrically connecting one of the plurality of pads to at least one of the plurality of terminal leads.
Dependencies are inferred from the claim text.