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US 2015/0084094 A1Published application
Scr component with temperature-stable characteristics
AssigneeSTMicroelectronics (Tours) SAS
InventorSamuel Menard
Life of this patent
Estimating the term…
Abstract
An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode.
Claims14
An SCR-type component of vertical structure, comprising:
- a silicon region of a first conductivity type formed in a silicon layer of the second conductivity type;
- a main upper electrode formed on the silicon region of the first conductivity type,
- wherein said silicon of the first conductivity type is interrupted by:
- first areas formed by the material of said silicon layer which are in contact with said main upper electrode, and
- second areas formed by resistive porous silicon which are also in contact with said main upper electrode and extend between said silicon layer and said main upper electrode.
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A method of, comprising:
- forming a silicon region of a first conductivity type in a silicon layer of a second conductivity type, wherein said silicon region is interrupted in areas;
- forming a peripheral silicon wall of the second conductivity type;
- depositing a masking layer on an upper surface, said masking layer including openings which expose at least on of said areas and the peripheral wall;
- plunging in a first electrolytic baths contacting the upper surface;
- plunging in a second electrolytic bath contacting a lower surface opposite the upper surface;
- wherein both plungings include a positive electrode and a negative electrode;
- and
- applying a voltage between the positive electrode and the negative electrode to have a current flow in the peripheral wall, with a portion of the current flowing in said silicon layer and through said areas to convert the silicon layer in said areas to a resistive porous silicon region.
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An integrated component, comprising:
- a multi-layer semiconductor substrate including a top semiconductor layer having a first conductivity type and having an upper surface;
- a plurality of regions formed in the top semiconductor layer having a second conductivity type, said regions extending into the top layer from the top surface;
- and
- a plurality of porous silicon regions formed in the top semiconductor layer, said porous silicon regions extending into the top layer from the top surface positioned between and in contact with first pairs of said regions having the second conductivity type.
1 more element
Dependencies are inferred from the claim text.