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US 2015/0084000 A1Published application
Forming A Non-Planar Transistor Having A Quantum Well Channel
AssigneeIntel Corporation
InventorsChi On Chui, Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
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Abstract
In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
Claims15
An apparatus comprising:
- a substrate;
- a semiconductor fin formed on the substrate, the semiconductor fin providing a channel region for a non-planar field effect transistor (FET);
- a first semiconductor layer adjacent the semiconductor fin, wherein the first semiconductor layer includes a higher bandgap than a bandgap of the semiconductor fin;
- a second semiconductor layer adjacent the first semiconductor layer;
- and
- a dielectric layer adjacent the second semiconductor layer.
3 more elements
A method comprising:
- forming a semiconductor fin on a substrate, the semiconductor fin providing a channel region for a non-planar field effect transistor (FET);
- forming a first semiconductor layer adjacent the semiconductor fin, wherein the first semiconductor layer includes a higher bandgap than a bandgap of the semiconductor fin;
- forming a second semiconductor layer adjacent the first semiconductor layer;
- and
- forming a dielectric layer adjacent the second semiconductor layer.
2 more elements
A method comprising:
- forming a buried oxide layer including silicon dioxide directly on a substrate;
- forming a non-planar silicon on insulator (SOI) core directly on the buried oxide layer, the non-planar SOI core formed of a silicon fin on the buried oxide layer having a width much less than an extent of the buried oxide layer, the silicon fin providing a channel region for a non-planar field effect transistor (FET);
- forming a quantum well (QW) layer around the non-planar SOI core, wherein the QW layer is formed of silicon germanium (SiGe) having a Ge concentration of at least approximately 10%, wherein the QW layer is compressive strained and having a smaller bandgap than the non-planar SOI core;
- and
- forming a silicon layer around the QW layer, wherein the silicon layer has a smaller bandgap than the SOI core and a larger bandgap than the QW layer.
2 more elements
Dependencies are inferred from the claim text.