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US 2015/0040136 A1Published application
System constraints-aware scheduler for heterogeneous computing architecture
AssigneeTexas Instruments Incorporated
InventorsKatrin Matthes, Damien Ramonda
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Abstract
Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters.
Claims20
A processor, comprising:
- a plurality of processor cores, each of which is arranged to perform processing tasks, and wherein at least one of the processor cores is of a different architecture than the other core(s);
- a scheduler that is arranged to receive task identifiers of respective processing tasks from a task queue and to allocate a selected core of the processor cores for each respective processing task received from the task queue;
- and
- a hint generator that is arranged to monitor one or more performance constraint parameters of the processor during operation of the processor and to generate a hint in response to the monitored one or more performance parameters, wherein the scheduler is arranged to allocate the respective processing task from the task queue to the selected core in response to the generated hint.
1 more element
A scheduling system, comprising:
- a scheduler that is communicatively coupled with a plurality of heterogeneous processor cores and with a task queue including one or more processing tasks, and wherein the scheduler is arranged to allocate the processing task from the task queue to a selected processor core of the plurality of processor cores based on a heuristic function and a load balancing mechanism;
- and
- a hint generator that is arranged to monitor one or more predetermined performance constraint parameters of the processor during operation of the scheduler and to generate a hint for biasing a selection of a core type of the plurality of heterogeneous processor cores in response to the monitored one or more performance parameters, wherein the generated hint is arranged to bias a selection of a core type of the plurality of heterogeneous processor cores, and wherein the scheduler is arranged to allocate the selected core of the processor cores in accordance with the generated hint.
A method, comprising:
- receiving from a task queue a succession of processing tasks for execution upon a plurality of heterogeneous processor cores in a processor, each of which is arranged to perform the respective processing tasks, wherein at least one of the processor cores is heterogeneous with respect to the architecture of at least one other of the processor cores, and wherein each processing task is associated with a respective task identifier;
- monitoring one or more performance constraint parameters of the processor during operation of the processor;
- generating a hint in response to comparing a first monitored performance constraint parameter with a first related system constraint setting, wherein the generated hint is arranged to bias a selection of a core type of the plurality of heterogeneous processor cores;
- and
- allocating each respective processing tasks to a selected processing core that is selected in response to a core type.
2 more elements
Dependencies are inferred from the claim text.