Multi-patterning mask decomposition method and system

A routing method, comprising:

• providing a portion of a layout of a single layer of an integrated circuit to be multi-patterned, the portion of the layout having a plurality of patterns representing circuit elements, the patterns including lines and divided into at least a first group and a second group, first group to be patterned on the single layer by a first mask in a first process, the second group to be patterned on the single layer by a second mask in a second process, wherein a line width bias of the second process is different from a line width bias of the first process;
• identifying an additional pattern of the layout separated from a nearest neighboring one of the plurality of patterns by at least a threshold distance;
• computing, in a processor, a first resistance (R) or resistance-capacitance (RC) cost of assigning the additional pattern to the first mask, and a second R or RC cost of assigning the additional pattern to the second mask, the computing based on a respective spacing relationship between each respective portion of the additional pattern and any adjacent pattern within the plurality of patterns on either or both sides of that portion;
• assigning the additional pattern to the first mask if the first R or RC cost is lower than the second R or RC cost, and
• assigning the additional pattern to the second mask if the second R or RC cost is lower than the first R or RC cost.

A system, comprising:

• a non-transitory, machine readable storage medium encoded with data representing a portion of a layout of a single layer of an integrated circuit to be multi-patterned, the portion of the layout having a plurality of patterns representing circuit elements, the patterns including lines and divided into at least a first group and a second group, each of the first and second groups to be patterned on the single layer by a respectively different one of a first mask in a first process or a second mask in a second process, wherein a line width bias of the second process is different from a line width bias of the first process;
• and
• a processor coupled to access the storage medium, the processor programmed to perform a method comprising:
• for each respective portion of each one of the plurality of patterns, determining a spacing relationship between that portion of that pattern and any adjacent pattern on either or both sides of that pattern;
• computing, in a processor, a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second C, R or RC cost of assigning the first group to the second mask and the second group to the first mask, the computing based on the spacing relationships;
• assigning, by the processor, the first group to the first mask and the second group to the second mask if the first C, R or RC cost is lower than the second C, R or RC cost, and
• assigning, by the processor, the first group to the second mask and the second group to the first mask if the first C, R or RC cost is higher than the second C, R or RC cost.